1. Field of the Invention
The present invention relates to a method of manufacturing a circuit board and the circuit board, and in particular, to a method of manufacturing a circuit board having an electro-conductive layer extended through a semiconductor substrate, and the circuit board.
2. Description of Related Art
As a result of expanded capacity of memory and more advanced functionalization of LSI, LSI chips having a plurality of semiconductor chips stacked therein have been developed (see Japanese Unexamined Patent Application Publications No. 2004-228598 (hereinafter referred to as “Patent Document 1”) and No. 2005-072596 (hereinafter referred to as “Patent Document 2”), for example). In the stacked chips at present, connection between the semiconductor chips is established by forming through-holes in a silicon (Si) substrate, filling the through-holes with an electro-conductive layer, and using fine bumps. Contact with the electro-conductive layer in the through-holes herein is established by adopting a method of carving out the electro-conductive layer by back grinding (BGR) (see Japanese Unexamined Patent Application Publication No. 2005-191255 (hereinafter referred to as “Patent Document 3”, for example), or a method of etching back the Si substrate from the back surface so as to expose the electro-conductive layer.
A known method of manufacturing a circuit board will be explained, referring to FIG. 6A to FIG. 10.
First, as shown in FIG. 6A, a SiO2 film 12′ serving as a hard mask is formed on a semiconductor substrate 11 composed of a Si wafer having elements such as transistors. Next, a resist pattern R1′ for forming through-holes in the semiconductor substrate 11 is formed on the SiO2 film 12′ by an existing photolithographic technique.
Next, as shown in FIG. 6B, the SiO2 film 12′ (see FIG. 6A) is patterned through the resist pattern R1′ used as a mask, to thereby form a hard mask 12. Next, a plurality of holes 13′ are formed in the semiconductor substrate 11 as being opened toward the surface thereof, by etching through the resist pattern R1′ and the hard mask 12 used as masks. In this process, variation in depth of the holes 13′ as large as 3 μm or more may be generated over the surface of the semiconductor substrate 11. This appears herein that the holes 13′ formed in the edge portion of the semiconductor substrate 11 are shallower by 3 μm or around than the holes 13′ formed in the center portion, wherein the shallowest hole 13′ is denoted as a hole 13a′, and the deepest hole 13′ is denoted as a hole 13b′. Thereafter, the resist pattern R1′ is removed.
Next, as shown in FIG. 7D, an insulating film 14 composed of SiO2 is formed on the hard mask 12 by chemical vapor deposition (CVD), so as to cover the inner wall of the holes 13′.
Then, as shown in FIG. 7E, a barrier film 15a, showing blocking performance against diffusion of Cu to be filled later in the holes 13′, is formed on the insulating film 14 so as to cover the inner walls of the holes 13′ having the insulating film 14 preliminarily formed thereto. Next, a Cu layer 15b is formed on the barrier film 15a so as to fill up the holes 13′ having the barrier film 15a preliminarily formed therein. By this process, the holes 13′ are filled with a first electro-conductive layer 15 composed of the barrier film 15a and the Cu layer 15b. 
Next, as shown in FIG. 7F, the first electro-conductive layer 15 is removed by chemical mechanical polishing (CMP) until the surface of the insulating film 14 is exposed. Thereafter, although not shown here, an interlayer insulating layer is formed on the first electro-conductive layer 15 and the insulating film 14, and interconnections are formed.
Next, as shown in FIG. 8G, the back surface of the semiconductor substrate 11 is polished. In this exemplary case, the back surface of the semiconductor substrate 11 is polished until the surface of the insulating film 14 is exposed. The insulating film 14 covers the first electro-conductive layer 15 formed in the shallowest holes 13a′ formed in the edge portion. In this process, the first electro-conductive layer 15 in the holes 13′ differed in the depth from the holes 13a′ by the thickness of the insulating film 14 or larger, is exposed and polished. For example, in the deepest holes 13b′ formed in the center portion, also Cu layer 15b is exposed and polished.
Next, as shown in FIG. 8H, the semiconductor substrate 11 is selectively etched from the back surface, so as to allow the first electro-conductive layer 15 covered with the insulating film 14 in the holes 13a′ to project out from the back surface of the semiconductor substrate 11. In this process, the first electro-conductive layer 15 in the holes 13, differed in the depth from the holes 13a′ by the thickness of the insulating film 14 or larger, are projected to be exposed. Thereafter, as shown in FIG. 8I, an insulating film 16 composed of SiO2 is formed on the back surface of the semiconductor substrate 11, so as to cover the projections.
FIG. 9J shows an enlarged view of essential portions of the shallowest hole 13a′ formed in the edge portion and the deepest hole 13b′ formed in the center portion. As illustrated in the drawing, the insulating film 16 is removed by CMP, until the surface of the first electro-conductive layer 15 in the hole 13a′ is exposed, more specifically until the surface of the barrier film 15a is exposed. In the hole 13b′ herein, the Cu layer 15b is exposed.
Next, as shown in FIG. 9K, a barrier film 17a is formed on the back surface of the semiconductor substrate 11 as well as on the first electro-conductive layer 15. Next, as shown in FIG. 9L, a resist pattern R2′ is formed on the barrier film 17a, and as shown in FIG. 10, the barrier film 17a is patterned by etching through the resist pattern R2′ (see FIG. 9L) used as a mask. Thereafter, a Cu layer 17b is formed on the barrier film 17a, to thereby form a rear interconnect composed of the second electro-conductive layer 17 having the barrier film 17a and the Cu layer 17b stacked therein.
As described in the above, a circuit board having through-hole electrodes composed of the first electro-conductive layer 15 in the semiconductor substrate 11 is formed.